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| rev. 0.5 november 2007 1 of 31 ddr3 sdram unbuffered sodimm * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to ch ange without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, crit ical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any gov- ernmental procurement to which spec ial terms or provisions may apply. ddr3 sdram specification 204pin unbuffered sodimm based on 1gb d-die 64-bit non-ecc (rohs compliant)
rev. 0.5 november 2007 2 of 31 ddr3 sdram unbuffered sodimm 1.0 ddr3 unbuffered sodimm ordering information ............... .............. .............. .............. .............4 2.0 key features ......... ................ ................ .............. .............. .............. ............... ............ ........... ........4 3.0 address configuration .... ................. ................ ................ ................. ................ ............... ............4 4.0 x64 dimm pin configurati ons (front side/back side) .. ............... ................. ................ .............5 5.0 pin description ............ ................ ................ ................. ................ ................. ............. .......... ........6 6.0 on dimm thermal sensor .. ................ ................ ................. ................ ................. ................ ........6 7.0 input/output functional description ................ .............. .............. ............... .............. .............. ...7 8.0 functional block diagram: .. ............... ................ ................. ................ ................. ............... ........ 8 8.1 512mb, 64mx64 modu le(populated as 1 ra nk of x16 ddr3 sdrams) ................ ............ ............ ..........8 8.2 1gb, 128mx64 modu le(populated as 2 rank of x16 ddr3 sdrams) ............... .............. .............. ......... 9 8.3 2gb, 256mx64 module(populated as 2 rank of x8 ddr3 sdrams) ............. .............. .............. ...........10 9.0 absolute maximum ratings ................. ................. ................ ................. ................ ............... .....11 9.1 absolute maximum dc ratings ................ ................ .............. .............. .............. .............. ...........11 9.2 dram component operating temperature range ............. ................ ................. ................ ...........11 10.0 ac & dc operating conditions ..... ................ ................ .............. ............... .............. ............. ..11 10.1 recommended dc operating conditions (sstl - 15) ............... ............... .............. .............. ........11 11.0 ac & dc input measuremen t levels ............... ................. ................ .............. .............. ...........12 11.1 ac and dc logic input levels for single-ended signals ................... ................. ................ ...........12 11.2 differential swing requirement for differntial signals ............... ............... .............. .............. ........13 11.2.1 sing le-ended requirements for differential signals ................ ................. ................ .............14 11.3 ac and dc logic input levels for differential signals ................ ............... .............. .............. ........15 11.4 differential input cross point voltage ............... ................. ................ .............. .............. ...........15 11.5 slew rate definiti on for single ended input signals ................ .............. .............. .............. ...........16 11.5.1 input slew rate for input setup time (tis) and data setup time (tds) ................. ............ ......16 11.5.2 input slew rate for input hold time (tih) and data hold time (tdh) ............. .............. ...........16 11.6 slew rate definition for differential input signals .............. ................. ................ .............. ...........16 12.0 ac and dc output measurement le vels ............. .............. .............. .............. .............. ...........17 12.1 single ended ac and dc output levels ................... .............. ............... .............. .............. ........17 12.2 differential ac and dc output levels ............... ................. ................ .............. .............. ...........17 12.3.single ended output slew rate ................. ................. ................ ................. ................ .............18 12.4 differential output slew rate ................ ................ .............. .............. .............. .............. ...........18 13.0 idd specification......... ................ ................ ................. ................ ................. .............. ......... ......19 13.1 idd specification ................ ................. ................ .............. .............. .............. .............. ...........20 14.0 input/output capacitance ................ ................ ................. ................ ................. ............... .......21 14.1. 1rx16 512mb sodimm ............. ................ ................. ................ ................. ................ .............21 14.2. 2rx16 1gb sodimm ................ ................ ................. ................ ................. ................ .............21 14.3. 2rx8 2gb sodimm ................ ................ .............. .............. .............. .............. .............. ...........21 15.0 electrical characteristics and ac timing .......... ................ .............. .............. .............. ...........22 15.1 refresh parameters by device density ................. ................ .............. .............. .............. ...........22 15.2 ddr3 sdram trcd, trp and trc .............. ................. ................ ................. ................ .............22 15.3 timing parameters for ddr 3-800, ddr3-1066 and ddr3-1333 .................. .............. .............. ........24 16.0 physical dimensions : .. ................. ................ ................ ................. ................ ............... ..........29 16.1 64mbx16 based 64mx64 module(1 rank) ................ .............. .............. .............. .............. ...........29 16.2 64mbx16 based 128mx64 module(2 ranks) ................. ................ ................. ................ .............30 16.3 128mbx8 based 256mx64 module(2 ranks) ................. ................ ................. ................ .............31 table contents rev. 0.5 november 2007 3 of 31 ddr3 sdram unbuffered sodimm revision history revision month year history 0.5 november 2007 - first release rev. 0.5 november 2007 4 of 31 ddr3 sdram unbuffered sodimm ? jedec standard 1.5v 0.075v power supply ? vddq = 1.5v 0.075v ? 400 mhz f ck for 800mb/sec/pin, 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin ? 8 independent internal bank ? programmable cas latency: 6,7,8,9 ? programmable additive latency(posted cas ) : 0, cl - 2, or cl - 1 clock ? programmable cas write latency(cwl) = 5(ddr3-800), 6(ddr3-1066), 7(ddr3-1333) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with st arting address ?000? only), 4 with tccd = 4 which does not al low seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data strobe ? internal(self) calibration : internal self ca libration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? average refresh period 7.8us at lower then t case 85 c, 3.9us at 85 c < t case 95 c ? asynchronous reset speed ddr3-800 ddr3-1066 ddr3-1333 unit 6-6-6 7-7-7 8-8-8 9-9-9 tck(min) 2.5 1.875 1.5 ns cas latency 6 789tck trcd(min) 15 13.125 15 13.5 ns trp(min) 15 13.125 15 13.5 ns tras(min) 37.5 37.5 37.5 36 ns trc(min) 52.5 50.625 52.5 49.5 ns 2.0 key features * ## : f7 / f8 / g8 / h9 part number density organization component composition number of rank height m471b6474dz1-cf7/f8/g8/h9 512mb 64mx64 64mx16(k4b1g1646d-hc##)*4 1 30mm m471b2874dz1-cf7/f8/g8/h9 1gb 128mx64 64mx16(k4b1g1646d-hc##)*8 2 30mm m471b5673dz1-cf7/f8/g8/h9 2gb 256mx64 128mx8(k4b1g0846d-hc##)*16 2 30mm organization row address column address bank address auto precharge 64x16(1gb) based module a0-a12 a0-a9 ba0-ba2 a10/ap 128x8(1gb) based module a0-a13 a0-a9 ba0-ba2 a10/ap 1.0 ddr3 unbuffered sodimm ordering information 3.0 address configuration rev. 0.5 november 2007 5 of 31 ddr3 sdram unbuffered sodimm note : 1. nc = no connect, nu = not useable, rfu = reserved future use 2. test(pin 125) is reserved for bus analysis probes and is nc on normal memory modules. 3. this address might be connected to nc balls of the drams ( depending on density); either way they will be connected to the te rmination resistor. pin front pin back pin front pin back pin front pin back 1 v refdq 2 v ss 71 v ss 72 v ss 139 v ss 140 dq38 3 v ss 4 dq4 key 141 dq34 142 dq39 5dq06dq573cke074cke1 143 dq35 144 v ss 7dq18 v ss 75 v dd 76 v dd 145 v ss 146 dq44 9 v ss 10 dqs0 77 nc 78 a15 3 147 dq40 148 dq45 11 dm0 12 dqs 079 ba2 80 a14 3 149 dq41 150 v ss 13 v ss 14 v ss 81 v dd 82 v dd 151 v ss 152 dqs 5 15 dq2 16 dq6 83 a12/bc 84 a11 153 dm5 154 dqs5 17 dq3 18 dq7 85 a9 86 a7 155 v ss 156 v ss 19 v ss 20 v ss 87 v dd 88 v dd 157 dq42 158 dq46 21dq822dq1289a890a6159dq43160dq47 23dq924dq1391a592a4161 v ss 162 v ss 25 v ss 26 v ss 93 v dd 94 v dd 163 dq48 164 dq52 27 dqs 1 28 dm1 95 a3 96 a2 165 dq49 166 dq53 29 dqs1 30 reset 97 a1 98 a0 167 v ss 168 v ss 31 v ss 32 v ss 99 v dd 100 v dd 169 dqs 6 170 dm6 33 dq10 34 dq14 101 ck0 102 ck1 171 dqs6 172 v ss 35 dq11 36 dq15 103 ck 0 104 ck 1 173 v ss 174 dq54 37 v ss 38 v ss 105 v dd 106 v dd 175 dq50 176 dq55 39 dq16 40 dq20 107 a10/ap 108 ba1 177 dq51 178 v ss 41 dq17 42 dq21 109 ba0 110 ras 179 v ss 180 dq60 43 v ss 44 v ss 111 v dd 112 v dd 181 dq56 182 dq61 45 dqs 246 dm2 113 we 114 s 0 183 dq57 184 v ss 47 dqs2 48 v ss 115 cas 116 odt0 185 v ss 186 dqs 7 49 v ss 50 dq22 117 v dd 118 v dd 187 dm7 188 dqs7 50 dq18 52 dq23 119 a13 3 120 odt1 189 v ss 190 v ss 53 dq19 54 v ss 121 s 1 122 nc 191 dq58 192 dq62 55 v ss 56 dq28 123 v dd 124 v dd 193 dq59 194 dq63 57 dq24 58 dq29 125 test 126 v ref ca 195 v ss 196 v ss 59 dq25 60 v ss 127 v ss 128 v ss 197 sa0 198 event 61 v ss 62 dqs 3 129 dq32 130 dq36 199 v ddspd 200 sda 63 dm3 64 dqs3 131 dq33 132 dq37 201 sa1 202 scl 65 v ss 66 v ss 133 v ss 134 v ss 203 v tt 204 v tt 67 dq26 68 dq30 135 dqs 4 136 dm4 69 dq27 70 dq31 137 dqs4 138 v ss samsung electronics co., ltd. reserves the right to change products and specifications without notice. 4.0 x64 dimm pin configurati ons (front side/back side) rev. 0.5 november 2007 6 of 31 ddr3 sdram unbuffered sodimm *the vdd and vddq pins are tied common to a single power-plane on these desigus. pin name description number pin name description number ck0, ck1 clock inputs, positive line 2 dq0-dq63 data input/output 64 ck 0, ck 1 clock inputs, negative line 2 dm0-dm7 data masks/ data strobes, termination data strobes 8 cke0, cke1 clock enables 2 dqs0-dqs7 data strobes 8 ras row address strobe 1 dqs 0-dqs 7 data strobes complement 8 cas column address strobe 1 reset reset pin 1 we write enable 1 test logic analyzer specific test pin (no connect on sodimm) 1 s 0, s 1 chip selects 2 event temperature event pin 1 a0-a9, a11, a13-a15 address inputs 14 v dd core and i/o power 18 a10/ap address input/autoprecharge 1 v ss ground 52 a12/bc address input/burst chop 1 v refdq v refca input/output reference 2 ba0-ba2 sdram bank addresses 3 v ddspd spd and temp sensor power 1 odt0, odt1 on-die termination control 2 v tt termination voltage 2 scl serial presence detect (spd) cloc k input 1 nc reserved for future use 2 sda spd data input/output 1 total 204 sa0-sa1 spd address 2 5.0 pin description event v ddspd scl sda sa0 sa1 vss v ddspd event scl sda spd with integrated ts sa0 sa1 sa2 vss 6.0 on dimm thermal sensor temperature sensor characteristics grade range temperature sensor accuracy units notes min. typ. max. c 75 < ta < 95 +/- 1.0 +/- 2.0 c 40 < ta < 125 +/- 2.0 +/- 3.0 -20 < ta < 125 +/- 3.0 +/- 4.0 resolution 0.25 c /lsb rev. 0.5 november 2007 7 of 31 ddr3 sdram unbuffered sodimm symbol type function ck0-ck1 ck0 -ck1 input the system clock inputs. all address and command li nes are sampled on the cross point of the rising edge of ck and falling edge of ck. a delay locked loop (dll) circui t is driven from the clock inputs and output timing for read operati ons is synchronized to the input clock. cke0-cke1 input activates the ddr3 sdram ck signal when high and deactivate s the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s 0-s 1 input enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1. r as , cas , we input when sampled at the cross point of t he rising edge of ck and falling edge of ck , signals cas , r as , and we define the operation to be executed by the sdram. ba0-ba2 input selects which ddr3 sdram in ternal bank of eight is activated. odt0-odt1 input asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr3 sdram mode register. a0-a9, a10/ap, a11 a12/bc a13-a15 input during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjuncti on with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pr echarged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burst chop (on-thefly) will be performed (high, no burst chop; low, burst chopped) dq0-dq63 i/o data input/output pins. dm0-dm7 input the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs0-dqs7 dqs 0-dqs 7 i/o the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdrams and is sent at the leading edge of the data window. dqs signals are complements, and timing is re lative to the crosspoint of respective dqs and dqs . v dd ,v ddspd, v ss supply power supplies for core, i/o, serial presen ce detect, temp sensor, and ground for the module. v refdq, v refca supply reference voltage for sstl15 inputs. sda i/o this is a bidirectional pin used to transfer data into or out of the spd eeprom and temp sensor. a resistor must be connected from the sda bus line to vddspd on the system planar to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom and temp sensor. sa0-sa1 input address pins used to select the seri al presence detect and temp sensor base address. test i/o the test pin is reserved for bus analysis tools and is not connected on normal memory modules event wire-or out the event pin is reserved for use to flag critical module temperature. a resistor may be connected from event bus line to v ddspd on the system planar to act as a pullup. reset input reset in active low this signal resets the ddr3 sdram 7.0 input/output functional description rev. 0.5 november 2007 8 of 31 ddr3 sdram unbuffered sodimm 8.1 512mb, 64mx64 module (populated as 1 rank of x16 ddr3 sdrams) s 0 ras cas we ck0 ck0 cke0 odt0 a[12:0] /ba[2:0] dqs0 dqs 0 dm0 ldqs ldqs udqs udqs dq[8:15] d0 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[0:7] dqs1 dqs 1 dm1 dq[8:15] dqs2 dqs 2 dm2 ldqs ldqs udqs udqs dq[8:15] d1 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[16:23] dqs3 dqs 3 dm3 dq[24:31] dqs4 dqs 4 dm4 ldqs ldqs udqs udqs dq[8:15] d2 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[32:39] dqs5 dqs 5 dm5 dq[40:47] dqs6 dqs 6 dm6 ldqs ldqs udqs udqs dq[8:15] d3 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[48:55] dqs7 dqs 7 dm7 dq[56:63] vtt v dd rank0 a0 a1 a2 sa0 sa1 scl sda event scl te m p s e n s o r (with spd) the spd may be integrated with the temp sensor or may be a separate component. event vtt v ss v dd d0 - d3 v ref ca v dd spd spd/ts ck0 v ref dq d0 - d3 d0 - d3 d0 - d3, spd, temp sensor v tt ck0 ck1 ck 1 odt1 s1 v tt d0 - d3 d0 - d3 terminated near card edge nc nc event reset temp sensor d0 - d3 8.0 functional block diagram: v tt d3 d2 d1 d0 address and controllines note : 1. dq wiring may differ from that shown however ,dq, dm, dqs and dqs relationships are maintained as shown rev. 0.5 november 2007 9 of 31 ddr3 sdram unbuffered sodimm 8.2 1gb, 128mx64 module (populated as 2 rank of x16 ddr3 sdrams) s 0 ras cas we ck0 ck0 cke0 odt0 a[12:0] /ba[2:0] s 1 ck1 ck1 cke1 odt1 dqs0 dqs 0 dm0 ldqs ldqs udqs udqs dq[8:15] d0 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[0:7] dqs1 dqs 1 dm1 dq[8:15] ldqs ldqs udqs udqs dq[8:15] d4 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dqs2 dqs 2 dm2 ldqs ldqs udqs udqs dq[8:15] d1 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[16:23] dqs3 dqs 3 dm3 dq[24:31] ldqs ldqs udqs udqs dq[8:15] d5 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dqs4 dqs 4 dm4 ldqs ldqs udqs udqs dq[8:15] d2 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[32:39] dqs5 dqs 5 dm5 dq[40:47] ldqs ldqs udqs udqs dq[8:15] d6 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dqs6 dqs 6 dm6 ldqs ldqs udqs udqs dq[8:15] d3 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% dq[48:55] dqs7 dqs 7 dm7 dq[56:63] ldqs ldqs udqs udqs dq[8:15] d7 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] ldm udm 240 ? 1% vtt v dd vtt v dd vtt rank0 rank1 note : 1. dq wiring may differ from that shown however ,dq, dm, dqs and dqs relationships are maintained as shown a0 a1 a2 sa0 sa1 scl sda v ss v dd d0 - d7 v ref ca v dd spd spd/ts event ck0 v ref dq d0 - d7 d0 - d7 d0 - d7, spd, temp sensor scl te m p s e n s o r (with spd) the spd may be integrated with the temp sensor or may be a separate component. event v tt ck1 ck 0 ck 1 event reset v tt d4 - d7 d0 - d3 d0 - d3 d4 - d7 temp sensor d0 - d7 v tt v4 v3 v2 v1 d7 d6 d5 d4 v tt v4 v3 v2 v1 d3 d2 d1 d0 address and controllines rev. 0.5 november 2007 10 of 31 ddr3 sdram unbuffered sodimm v7 v8 v5 s1 ras cas we ck1 ck1 cke1 odt1 a[0:n] /ba[0:n] s 0 ck0 ck0 cke0 odt0 dqs3 dqs 3 dm3 dqs dqs d11 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% dq[24:31] d3 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% vtt v dd vtt rank0 rank1 note : 1. dq wiring may differ from that shown however ,dq, dm, dqs and dqs relationships are maintained as shown a0 a1 a2 sa0 sa1 scl sda v ss v dd d0 - d15 v ref ca v dd spd spd/ts event ck0 v ref dq d0 - d15 d0 - d15 d0 - d15, spd, temp sensor scl te m p s e n s o r (with spd) the spd may be integrated with the temp sensor or may be a separate component. event v tt ck1 ck 0 ck 1 event reset v tt d8 - d15 d0 - d7 d0 - d7 d8 - d15 temp sensor d0 - d7 v6 v2 v3 d6 d12 d3 d9 v tt address and controllines dqs dqs dq[0:7] dm dqs1 dqs 1 dm1 dqs dqs d1 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% dq[8:15] d9 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs0 dqs 0 dm0 dqs dqs d0 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% dq[0:7] d8 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs2 dqs 2 dm2 dqs dqs d2 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% dq[16:23] d10 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs dqs d11 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% d3 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs dqs d1 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% d9 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs dqs d0 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% d8 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs dqs d2 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 ? 1% d10 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 ? 1% dqs dqs dq[0:7] dm dqs4 dqs 4 dm4 dq[32:39] dqs6 dqs 6 dm6 dq[48:55] dqs7 dqs 7 dm7 dq[56:63] dqs5 dqs 5 dm5 dq[40:47] v dd d7 d5 d10 d8 v1 v4 v9 v7 v6 v9 v8 v4 v3 d15 d13 d2 d0 d14 d4 d11 d1 v1 v2 v5 v1 8.3 2gb, 256mx64 module (populated as 2 rank of x8 ddr3 sdrams) rev. 0.5 november 2007 11 of 31 ddr3 sdram unbuffered sodimm note : 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above t hose indicated in the operat ional sections of this s pecification is not implied. exposure to absolute maximum ra ting conditions for extended peri ods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all time s;and vref must be not greater than 0.6xvddq, when vdd and vddq a re less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes vdd voltage on vdd pin relative to vss -0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to vss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 1, 2 note : 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. for measurement condi tions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, t he dram case tem- perature must be maintained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaran- teed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reduc ing the refresh interval trefi to 3.9us. it is also possibl e to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. please refer to supplier data sheet and/or the dimm spd for option availability. b) if self-refresh operation is required in the extended temper ature range, then it is mandatory to either use the manual sel f-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the supplier data sheet and/or the dimm spd for auto self-refresh option availability, extended temperatur e range support and trefi requirements in the extended temperature range. symbol parameter rating unit notes t oper normal operating temperature range 0 to 85 c 1,2 extended temperature range (optional) 85 to 95 c 1,3 9.2 dram component operating temperature range 9.1 absolute maximum dc ratings 10.0 ac & dc operating conditions 10.1 recommended dc operating conditions (sstl - 15) note : 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.5 1.575 v 1,2 vddq supply voltage for output 1.425 1.5 1.575 v 1,2 9.0 absolute maximum ratings rev. 0.5 november 2007 12 of 31 ddr3 sdram unbuffered sodimm single ended ac and dc input levels note : 1. for dq and dm, v ref = v refdq . for input only pins except reset, or v ref = v refca 2. see "overshoot and undershoot specifications" on component datasheet 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than 1% vdd (for reference : approx. 15mv) 4. for reference : approx. vdd/2 15mv 5. single ended swing requirement for dqs - dqs is 350 mv(peak to peak). differentia l swing requirement for dqs - dqs is 700 mv(peak to peak). symbol parameter ddr3-800/1066/1333 unit notes min. max. v ih (dc) dc input logic high vref + 100 vdd mv 1 v il (dc) dc input logic low vss vref - 100 mv 1 v ih (ac) ac input logic high vref + 175 - mv 1,2 v il (ac) ac input logic low - vref - 175 mv 1,2 v ref dq (dc) i/o reference voltage(dq) 0.49*vddq 0.51*vddq v 3,4 v ref ca (dc) i/o reference voltage(cmd/add) 0.49*vddq 0.51*vddq v 3,4 the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrate in figure 1. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long per iod of time (e.g. 1 sec). this average has to meet the min/max requiremts in above table. furthermore vref(t) may temporarily deviate from vref(dc) by no more than 1% vdd. voltage vdd vss v ref ac-noise v ref (dc) v ref (dc)max vdd/2 v ref (dc)min time v ref (t) 11.1 ac and dc logic input levels for single-ended signals illustration of vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref" shall be understood as vref(dc), as defined in above figure. this clarifies, that dc-varia tions of vref affect the absolute voltage a signal has to reach to achieve a valid high or low le vel and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum po sition within the data-eye of the input signals. this also clarifies that the dram setup/hold specificati on and derating values need to include time and voltage associated wit h vref ac-noise. timing and voltage effects due to ac-noise on vref up to the specified li mit (+/-1% of vdd) are included in dram timings and their ass ociated deratings. 11.0 ac & dc input measurement levels rev. 0.5 november 2007 13 of 31 ddr3 sdram unbuffered sodimm definition of differntial ac-swing and "time above ac level tdvac differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs , dqsl - dqsl , dqsu - dqsu use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a si gnal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih(dc) max, vil(dc)min) fo r single-ended signals as we ll as the limitations for overshoot and undershoot. allowed time before ringback (tdvac) for clk - clk and dqs - dqs . symbol parameter ddr3-800 / 1066 / 1333 unit note min max vihdiff differential input high +0.2 note 3 v 1 vildiff differential input low note 3 -0.2 v 1 vihdiff(ac) differential input high ac 2 x (vih(ac)-vref) note 3 v 2 vildiff(ac) differential input low ac note 3 2 x (vref - vil(ac)) v 2 slew rate [v/ns] tdvac [ps] @ |vih/ldiff(ac)| = 350mv tdvac [ps] @ |vih/ldiff(ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - 11.2 differential swing requirement for differntial signals 0.0 tdvac vihdiff(ac) min vihdiff min vihdiff(dc) min vildiff(dc) max vildiff max vildiff(ac) max differential voltage half cycle time time tdvac ck - ck dqs - dqs rev. 0.5 november 2007 14 of 31 ddr3 sdram unbuffered sodimm single-ended requirement for differential signals. note that while add/cmd and dq signal requirements are with re spect to vref, the single-ended components of differential signal s have a requirement with respect to vdd/2; this is nominally the same. the transition of single-ended signals through the ac-levels i s used to measure setup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin has no bearin g on timing, but adds a restriction on the comm on mode charateristics of these signals. vdd or vddq vseh min vdd/2 or vddq/2 vsel max vseh vss or vssq vsel ck or dqs time 11.2.1 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , or dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels ( vih(ac) / vil(ac) ) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (approximately t he ac-levels ( vih(ac) / vil(ac) ) for dq signals) in every half-cycle prec eeding and foll owing a valid transition. note that the applicable ac-levels for add/cm d and dq?s might be different per speed-bi n etc. e.g. if vih1 50(ac)/vil150(ac) is used for add/cmd signals, then these ac-levels apply al so for the single-ended signals ck and ck each single ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu notes: 1. for ck, ck use vih/vil(ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) for add/cmd is based on vrefca; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. these values are not defined, how ever they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih(dc) max, vil(dc)min) fo r single-ended signals as well as the li mitations for overshoot and undershoot. symbol parameter ddr3-800/1066/1333 unit notes min max vseh single-ended high-level for strobes vih(ac)-vrefdq+vddq/2 note3 v 1, 2 single-ended high-level for ck, ck vih(ac)-vrefca+vddq/2 note3 v 1, 2 vsel single-ended low-level for strobes note3 vil(ac)+vrefdq-vddq/2 v 1, 2 single-ended low-level for ck, ck note3 vil(ac)+vrefca-vddq/2 v 1, 2 rev. 0.5 november 2007 15 of 31 ddr3 sdram unbuffered sodimm differential dc and ac input levels note : 1. refer to "overshoot and undershoot specifications" on component datasheet symbol parameter ddr3-800/1066/1333 unit notes min max vihdiff differential input logic high + 200 - mv 1 vildiff differential input logic low - - 200 cross point voltage for differential input signals (ck, dqs) note 1: extended range for vix is only allowed for clock and if single-ended clock input signals ck and ck are monotonic, have a single-ended swing vsel/vseh of at least vdd/2 +/-250 mv and if the differential slew rate of ck-ck is larger than 3 v/ns. symbol parameter ddr3-800/1066/1333 unit notes min max vix differential input cross point voltage relative to vdd/2 for ck/ck -150 150 mv -175 175 mv 1 vix differential input cross point voltage relative to vdd/2 for dqs/dqs -150 150 mv to guarantee tight setup and hold times as well as output skew para meters with respect to clock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the different ial input cross point voltage vix is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vdd ck , dqs vdd/2 ck, dqs vss v ix v ix v ix 11.4 differential input cross point voltage vix definition 11.3 ac and dc logic input levels for differential signals rev. 0.5 november 2007 16 of 31 ddr3 sdram unbuffered sodimm 11.5.1 input slew rate for input setu p time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil(ac)max. 11.5.2 input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first cr ossing of vref. hold (tih & tdh) nominal slew rate for a falling signal is defined as the slew rate between the la st crossing of vih(dc)min and the first c rossing of vref single ended input slew rate definition notes: this nominal slew rate app lies for linear signal waveforms. description measured defined by applicable for from to input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis,tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih,tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq < figure : input slew rate for setup> v swing(max) delta trs delta tfs v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ssq v swing(max) delta trh delta tfh < figure : input slew rate for hold> differential input slew rate definition note : the differential signal (i.e. ck - ck and dqs - dqs ) must be linear between these thresholds description measured defined by from to differential input slew rate for rising edge (ck- ck and dqs-dqs ) vildiffmax vihdiffmin vihdiffmin - vildiffmax delta trdiff differential input slew rate for falling edge (ck- ck and dqs-dqs ) vihdiffmin vildiffmax vihdiffmin - vildiffmax delta tfdiff 11.5 slew rate definition for single ended input signals 11.6 slew rate definition for differential input signals input nominal slew rate definition for singel ended signals differential input slew rate definition for dqs, dqs and ck, ck vihdiffmin v ref vildiffmax delta trdiff delta tfdiff rev. 0.5 november 2007 17 of 31 ddr3 sdram unbuffered sodimm single ended ac and dc output levels note : 1. the swing of +/-0.1xvddq is based on approximately 50% of t he static single ended output high or low swing with a driver imp edance of 34ohms and an effective test load of 25ohms to vtt=vddq/2. symbol parameter ddr3-800/1066/1333 units notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v v ol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v v oh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 v ol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 differential ac and dc output levels note : 1. the swing of +/-0.2xvddq is based on approximately 50% of t he static singel ended output high or low swing with a driver imp edance of 34ohms and an effective test load of 25ohms to vtt=vddq/2 at each of the differential outputs symbol parameter ddr3-800/1066/1333 units notes v ohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v 1 v oldiff(dc) ac differential output low measurement level (for output sr) -0.2 x vddq v 1 12.2 differential ac and dc output levels 12.1 single ended ac and dc output levels 12.0 ac and dc out put measurement levels rev. 0.5 november 2007 18 of 31 ddr3 sdram unbuffered sodimm v ddq v oh(ac) v ref v ol(ac) v ssq delta trs delta tfs 12.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for differential signals as shown in below table and figure. differential output slew rate definition differential output slew rate note : output slew rate is verified by design and ch aracterization, and may not be subject to production test. for ron=rzq/7 setting description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) delta trdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) delta tfdiff parameter symbol ddr3-800 ddr3-1066 ddr3-1333 units min max min max min max single ended output slew rate srqse 5 10 5 10 5 10 v/ns v ddq v ohdiff(ac) v ref v oldiff(ac) v ssq delta trdiff delta tfdiff single ended output slew rate definition differential output slew rate definition 12.3.single ended ou tput slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signals as show n in below table and figure. single ended output slew rate definition single ended output slew rate note : output slew rate is verified by design and char acterization, and may not be subject to production test. for ron=rzq/7 setting description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) delta trse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) delta tfse parameter symbol ddr3-800 ddr3-1066 ddr3-1333 units min max min max min max single ended output slew rate srqse 2.5 5 2.5 5 2.5 5 v/ns rev. 0.5 november 2007 19 of 31 ddr3 sdram unbuffered sodimm (idd values are for full operating range of voltage and temperature) symbol conditions max units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w tbd ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching tbd ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching;data bus inputs are switching tbd ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 8, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w tbd ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating tbd ma idd6et extended temperature range self-refresh current ; ck and ck at 0v; cke 0.2v; other control and address inputs are floating; data bus inputs are floating, pasr disabled, applicable for mr2 setting a6=0 and a7=1 tbd ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 8, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; tbd ma 13.0 idd specification rev. 0.5 november 2007 20 of 31 ddr3 sdram unbuffered sodimm m471b6474dz1 : 512mb (64mx64) module symbol f7 (ddr3 - 800 @ cl = 6) f8 (ddr3 - 1066 @ cl = 7) g8 (ddr3 - 1066 @ cl = 8) h9 (ddr3 - 1333 @ cl = 9) units notes idd0 tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd ma idd2p tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd ma idd3p tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd ma idd5b tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd ma idd6tc tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd ma m471b2874dz1 : 1gb (128mx64) module symbol f7 (ddr3 - 800 @ cl = 6) f8 (ddr3 - 1066 @ cl = 7) g8 (ddr3 - 1066 @ cl = 8) h9 (ddr3 - 1333 @ cl = 9) units notes idd0 tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd ma idd2p tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd ma idd3p tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd ma idd5b tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd ma idd6tc tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd ma 13.1 idd sp ecification m471b5673dz1 : 2gb (256mx64) module symbol f7 (ddr3 - 800 @ cl = 6) f8 (ddr3 - 1066 @ cl = 7) g8 (ddr3 - 1066 @ cl = 8) h9 (ddr3 - 1333 @ cl = 9) units notes idd0 tbd tbd tbd tbd ma idd1 tbd tbd tbd tbd ma idd2p tbd tbd tbd tbd ma idd2q tbd tbd tbd tbd ma idd2n tbd tbd tbd tbd ma idd3p tbd tbd tbd tbd ma idd3n tbd tbd tbd tbd ma idd4w tbd tbd tbd tbd ma idd4r tbd tbd tbd tbd ma idd5b tbd tbd tbd tbd ma idd6 tbd tbd tbd tbd ma idd6et tbd tbd tbd tbd ma idd6tc tbd tbd tbd tbd ma idd7 tbd tbd tbd tbd ma rev. 0.5 november 2007 21 of 31 ddr3 sdram unbuffered sodimm 14.1. 1rx16 512mb sodimm 14.2. 2rx16 1gb sodimm 14.3. 2rx8 2gb sodimm m471b6474dz1 parameter symbol ddr3-800 ddr3-1066 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m471b2874dz1 parameter symbol ddr3-800 ddr3-1066 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m471b5673dz1 parameter symbol ddr3-800 ddr3-1066 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf 14.0 input/output capacitance rev. 0.5 november 2007 22 of 31 ddr3 sdram unbuffered sodimm speed ddr3-800 ddr3-1066 ddr3-1333 units note bin (cl - trcd - trp) 6-6-6 7-7-7 8-8-8 9-9-9 parameter min min min min cl 6 789 tck trcd 15 13.13 15 13.5 ns trp 15 13.13 15 13.5 ns tras 37.5 37.5 37.5 36 ns trc 52.5 50.63 52.5 49.5 ns trrd [1kb] 10 7.5 7.5 6 ns trrd [2kb] 10 10 10 7.5 ns tfaw [1kb] 40 37.5 37.5 30 ns tfaw [2kb] 50 50 50 45 ns (0 c rev. 0.5 november 2007 24 of 31 ddr3 sdram unbuffered sodimm 15.3 timing parameters for ddr3-800, ddr3-1066 and ddr3-1333 timing parameters by speed bin speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max clock timing minimum clock cycle time (dll off mode) t ck(dll_off) 8 - 8 - 8 - ns 6 average clock period t ck(avg) see speed bins table ps f clock period t ck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width t ch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f average low pulse width t cl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 t ck(avg) f clock period jitter tjit (per) -100 100 -90 90 -80 80 ps clock period jitter during dll locking period tjit (per, lck) -90 90 -80 80 -70 70 ps cycle to cycle period jitter tjit (cc) 200 180 160 ps cycle to cycle period jitter during dll locking period tjit (cc, lck) 180 160 140 ps cumulative error across 2 cycles t err(2per) - 147 147 - 132 132 - 118 118 ps cumulative error across 3 cycles t err(3per) - 175 175 - 157 157 - 140 140 ps cumulative error across 4 cycles t err(4per) - 194 194 - 175 175 - 155 155 ps cumulative error across 5 cycles t err(5per) - 209 209 - 188 188 - 168 168 ps cumulative error across 6 cycles t err(6per) - 222 222 - 200 200 - 177 177 ps cumulative error across 7 cycles t err(7per) - 232 232 - 209 209 - 186 186 ps cumulative error across 8 cycles t err(8per) - 241 241 - 217 217 - 193 193 ps cumulative error across 9 cycles t err(9per) - 249 249 - 224 224 - 200 200 ps cumulative error across 10 cycles t err(10per) - 257 257 - 231 231 - 205 205 ps cumulative error across 11 cycles t err(11per) - 263 263 - 237 237 - 210 210 ps cumulative error across 12 cycles t err(12per) - 269 269 - 242 242 - 215 215 ps cumulative error across n = 13, 14 ... 49, 50 cycles t err(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max ps 24 absolute clock high pulse width t ch(abs) 0.43 0.43 0.43 t ck(avg) 25 absolute clock low pulse width t cl(abs) 0.43 0.43 0.43 t ck(avg) 26 data timing dqs,dqs to dq skew, per group, per access t dqsq - 200 - 150 - 125 - 100 dq output hold time from dqs, dqs t qh 0.38 - 0.38 - 0.38 - 0.38 - dq low-impedance time from ck, ck t lz(dq) -800 400 -600 300 -500 250 -450 225 dq high-impedance time from ck, ck t hz(dq) - 400 - 300 - 250 - 225 data setup time to dqs, dqs referenced to vih(ac)vil(ac) levels t ds(base) 75 - 25 - tbd - tbd data hold time to dqs, dqs referenced to vih(ac)vil(ac) levels t dh(base) 150 - 100 - tbd - tbd dq and dm input pulse width for each input t dipw 600 - 490 - 400 - data strobe timing dqs, dqs read preamble t rpre 0.9 - 0.9 - 0.9 - t ck 13, 19, g dqs, dqs differential read postamble t rpst 0.3 note1 0.3 note1 0.3 note1 t ck 11, 13, b dqs, dqs output high time t qsh 0.38 - 0.38 - 0.4 - t ck(avg) 13, g dqs, dqs output low time t qsl 0.38 - 0.38 - 0.4 - t ck(avg) 13, g dqs, dqs write preamble t wpre 0.9 - 0.9 - 0.9 - t ck dqs, dqs write postamble t wpst 0.3 - 0.3 - 0.3 - t ck dqs, dqs rising edge output access time from rising ck, ck t dqsck -400 400 -300 300 -255 255 ps 13,f dqs, dqs low-impedance time (referenced from rl-1) t lz(dqs) -800 400 -600 300 -500 250 ps 13,14,f dqs, dqs high-impedance time (referenced from rl+bl/ 2) t hz(dqs) - 400 - 300 - 250 ps 12,13,14 dqs, dqs differential input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs differential input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs, dqs rising edge to ck, ck rising edge t dqss -0.25 0.25 -0.25 0.25 -0.25 0.25 t ck(avg) c dqs,dqs faling edge setup time to ck, ck rising edge t dss 0.2 - 0.2 - 0.2 - t ck(avg) c dqs,dqs faling edge hold time to ck, ck rising edge t dsh 0.2 - 0.2 - 0.2 - t ck(avg) c rev. 0.5 november 2007 25 of 31 ddr3 sdram unbuffered sodimm timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max command and address timing dll locking time t dllk 512 - 512 - 512 - nck internal read command to precharge command delay t rtp max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e delay from start of internal write transaction to internal read command t wtr max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - max (4t ck ,7.5ns) - e,18 write recovery time t wr 15 - 15 - 15 - ns e mode register set command cycle time t mrd 4 - 4 - 4 - t ck(avg) mode register set command update delay t mod max (12t ck ,15ns) - max (12t ck ,15ns) - max (12t ck ,15ns) - cas# to cas# command delay t ccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time t dal(min) wr + roundup (t rp / t ck(avg) ) nck multi-purpose register recovery time t mprr 1 - 1 - 1 - nck active to precharge command period t ras 37.5 70,000 37.5 70,000 36 70,000 ns e active to active command period for 1kb page size t rrd max (4t ck ,10ns) - max (4t ck ,7.5ns) - max (4t ck ,6ns) - e active to active command period for 2kb page size t rrd max (4t ck ,10ns) - max (4t ck ,10ns) - max (4t ck ,7.5ns) - e four activate window for 1kb page size t faw 40 - 37.5 - 30 - ns e four activate window for 2kb page size t faw 50 - 50 - 45 - ns e command and address setup time to ck, ck referenced to vih(ac) / vil(ac) levels t is(base) 200 - 125 - 65 - ps b,16 command and address hold time from ck, ck referenced to vih(ac) / vil(ac) levels t ih(base) 275 - 200 - 140 - b,16 command and address setup time to ck, ck referenced to vih(ac) / vil(ac) levels t is(base) ac150 - - - - 65+125 - ps b,16,27 refresh timing 1gb refresh to refresh or refresh to active command interval t rfc 110 - 110 - 110 - ns average periodic refresh interval (0 c tcase 85 c ) t refi 7.8 7.8 7.8 us average periodic refresh interval (85 c tcase 95 c ) t refi 3.9 3.9 3.9 us calibration timing power-up and reset calibration time t zqiniti 512 - 512 - 512 - t ck normal operation full calibration time t zqoper 256 - 256 - 256 - t ck normal operation short calibration time t zqcs 64 - 64 - 64 - t ck 23 reset timing exit reset from cke high to a valid command t xpr max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - max(5t ck , t rfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll t xs max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - max(5t ck ,t rfc + 10ns) - exit self refresh to commands requiring a locked dll t xsdll t dllk (min) - t dllk (min) - t dllk (min) - t ck minimum cke low width for self refresh entry to exit timing t ckesr t cke (min) + 1t ck - t cke (min) + 1t ck - t cke (min) + 1t ck - valid clock requirement after self refresh entry (sre) t cksre max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) - valid clock requirement before self refresh exit (srx) t cksrx max(5t ck ,10ns) - max(5t ck ,10ns) - max(5t ck ,10ns) - rev. 0.5 november 2007 26 of 31 ddr3 sdram unbuffered sodimm timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max power down timing exit power down with dll on to any valid command;exit percharge power down with dll frozen to commands not requiring a locked dll t xp max (3t ck ,7.5ns) - max (3t ck ,7.5ns) - max (3t ck ,6ns) - exit precharge power down with dll frozen to commands requiring a locked dll t xpdll max (10t ck ,24ns) - max (10t ck ,24ns) - max (10t ck ,24ns) - 2 cke minimum pulse width t cke max (3t ck ,7.5ns) - max (3t ck ,5.625ns) - max (3t ck ,5.625ns) - command pass disable delay t cpded 1 - 1 - 1 - nck power down entry to exit timing t pd t cke (min) 9*t refi t cke (min) 9*t refi t cke (min) 9*t refi t ck 15 timing of act command to power down entry t actpden 1 - 1 - 1 - nck 20 timing of pre command to power down entry t prpden 1 - 1 - 1 - nck 20 timing of rd/rda command to power down entry t rdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bl4otf) t wrpden wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - wl + 4 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bl4otf) t wrapden wl + 4 +wr +1 - wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bl4mrs) t wrpden wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - wl + 2 +(t wr / t ck ) - nck 9 timing of wra command to power down entry (bl4mrs) t wrapden wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry t refpden 1 - 1 - 1 - 20,21 timing of mrs command to power down entry t mrspden t mod(min) - t mod(min) - t mod(min) - t ck odt timing odt high time without write command or with wirte com- mand and bc4 odth4 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt tum-on delay (power-down with dll frozen) t aonpd 1 9 1 9 1 9 ns asynchronous rtt tum-off delay (power-down with dll frozen) t aofpd 1 9 1 9 1 9 ns odt turn-on t aon -400 400 -300 30 -250 250 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff refer- ence t aof 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) 8,f rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 0.3 0.7 t ck(avg) f write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed t wlmrd 40 - 40 - 40 - t ck 3 dqs/dqs delay after tdqs margining mode is programmed t wldqsen 25 - 25 - 25 - t ck 3 setup time for tdqss latch t wls 325 - 245 - 195 - ps hold time of tdqss latch t wlh 325 - 245 - 195 - ps write leveling output delay t wlo 0 9 0 9 0 9 ns write leveling output error t wloe 0 2 0 2 0 2 ns rev. 0.5 november 2007 27 of 31 ddr3 sdram unbuffered sodimm jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input cl ock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges. ex) tmrd =4 [nck] means; if one mode register set command is registered at tm, anothe mode register set com mdn may be reg- istered at tm+4, even if (tm+4-tm ) is 4 x tck(avg) +terr(4per) min. specific note b these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the set up and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clo ck jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs (l/u)) crossing to its respec tive clock signal (ck, ck ) crossing. the spec val- ues are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), et c.), as these are relative to the clock signal crossing. that is, these parameters should be met w hether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l /u)0, dq(l/u)1, etc.) transition edge to its respective data str obe signal (dqs(l/u), dqs (l/u)) crossing. specific note e for these parameters, the ddr3 sdram device s upports tnparam [nck] = ru{ tparam [ns] / tc k(avg) [ns] }, which is in clock cycle s, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all i nput clock jitter specificat ions are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, the devic e will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter s pecifications are met, i.e. precharge command at tm and active command at tm+6 is valid ev en if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the inp ut clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has terr(mper),act,min = - 172 ps and terr(mper),act,max = + 193 ps, then tdqsck,min(derated) = tdqsck,min - terr(mper),act,max = - 400 ps - 193 ps = - 593 ps and tdqsck,max(derated) = tdqsck,max - terr(mper),act,min = 400 ps + 172 ps = + 572 ps. similarly, tlz(dq) for ddr3-800 derates to tlz(dq),min(derated) = - 800 ps - 1 93 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maxi mum measured value of terr(nper) where 2 <= n <= 12 specific note g when the device is operated with input clock jitter, this paramet er needs to be derated by the actual tjit(per),act of the inpu t clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has tc k(avg),act = 2500 ps, tjit(per),act,min = - 72 ps and tjit(per) ,act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck( avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps . similarly, tqh,min(der- ated) = tqh,min + tjit(per),act, min = 0.38 x tck(avg),act + tjit(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) rev. 0.5 november 2007 28 of 31 ddr3 sdram unbuffered sodimm timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation" 8. for definition of rtt turn-off time taof see "device operation". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum postamble is bound by thzdqs(max) 12. output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this pa rameter needs to be derated by tbd 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter <8, 9> for definition and measurement method. 15. trefi depends on toper 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate, note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). see "address/ command setup, hold and derating" on page 52. 17. tds(base) and tdh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, vref(dc)= vrefdq(dc). for input only pins except reset , vref(dc)=vrefca(dc). see "data setup, hold and slew rate derating" on page 58. 18. start of internal write transaction is definited as follows ; for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly) : rising clock edge 4 clock cycles after wl for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl 19. the maximum preamble is bound by tlzdqs(max) 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in pro gress, but power-down idd spec will not be applied until finishing those operations. 21. altough cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see "device operation". 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropri- ate interval between zqcs commands can be determined from these tables and other application specific parameters. one method fo r calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) for example, if tsens = 1.5% / c, vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling ed ge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edg e. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter- nate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 ~ ~ 128ms rev. 0.5 november 2007 29 of 31 ddr3 sdram unbuffered sodimm the used device is 64m x16 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g1646d - hc** 16.1 64mbx16 based 64mx64 module(1 rank) 0.25 max 2.55 detail b detail a 1.00 0.10 0.45 0.03 4.00 0.10 16.0 physical dimensions : 67.60 30.00 mm nom. spd 1.00 0.10 20.00 mm 3.00 0.10 ab m c 2x 4.00 0.10 0.10 ab m c 2x 1.80 (optional holes) 0.60 units : millimeters max 3.8 rev. 0.5 november 2007 30 of 31 ddr3 sdram unbuffered sodimm units : millimeters the used device is 64m x16 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g1646d - hc** 16.2 64mbx16 based 128mx64 module(2 ranks) 67.60 30.00 mm nom. spd max 3.8 1.00 0.10 20.00 mm 0.10 ab m c 2x 4.00 0.10 0.10 ab m c 2x 1.80 (optional holes) 0.25 max 2.55 detail b detail a 1.00 0.10 0.45 0.03 4.00 0.10 0.60 3.00 rev. 0.5 november 2007 31 of 31 ddr3 sdram unbuffered sodimm units : millimeters the used device is 128m x8 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g0846d - hc** 67.60 30.00 mm nom. spd max 3.8 1.00 0.10 20.00 mm 0.10 ab m c 2x 4.00 0.10 0.10 ab m c 2x 1.80 (optional holes) 0.25 max 2.55 detail b detail a 1.00 0.10 0.45 0.03 4.00 0.10 0.60 3.00 16.3 128mbx8 based 256mx64 module(2 ranks) |
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